Modelling of multi-layered power supply planes with vias

Author

Shih Yen Lee ; Yong Kee Yeo ; Mui Seng Yeo ; Iyer, Mahadevan K. ; Do, Nhon ; Wui Weng Wong

Author_Institution

Adv. Packaging Devlopment Support Dept., Inst. of Microelectron., Singapore, Singapore

fYear

2001

fDate

2001

Firstpage

69

Lastpage

72

Abstract

A 2-layered power plane modelling methodology based on transmission lines (TL) is used to model a commercial microprocessor package up to 10 GHz. Subsequently, a 3-layered power plane model is proposed. This model was further modified to model 3-layered power distribution planes with vias. Comparisons with the measurements showed that the modified model was able to offer accurate simulation results up to 10 GHz

Keywords

circuit simulation; integrated circuit modelling; integrated circuit packaging; microprocessor chips; power supply circuits; printed circuit testing; transmission line theory; 10 GHz; measurements; microprocessor package; modelling; multi-layered power supply planes; power distribution planes; power plane model; power supply plane vias; simulation; transmission lines based power plane modelling methodology; Dielectric losses; Dielectric substrates; Frequency dependence; Microprocessors; Packaging; Power distribution; Power supplies; Power system transients; Power transmission lines; Transmission line theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2001

Conference_Location

Cambridge, MA

Print_ISBN

0-7803-7024-4

Type

conf

DOI

10.1109/EPEP.2001.967613

Filename

967613