Exploration of sign precomputation-based CORDIC in reconfigurable systems

Presented is an analysis of standard CORDIC implementations with sign precomputation mapped onto four modern Xilinx Field-Programmable Gate Arrays (FPGA) families, Virtex-4, -5, -6 and Spartan-6. Three methods of sign precomputation, P-CORDIC, Flat-CORDIC and Para-CORDIC have been proposed in previous literature as parallel methods for reducing CORDIC algorithm logic delay when implemented on an Application Specific Integrated Circuits (ASICs). However, little analysis exists on reconfigurable implementations where one major algorithm optimization design goal is to reduce interconnection delay. All three sign precomputation CORDIC techniques are shown to improve delay and logic utilization when compared with standard CORDIC. On state-of-the-art FPGAs, such as Virtex-6, P-CORDIC is found to perform best; on older devices, such as Virtex-4, Flat-CORDIC has the best performance. On in-between FPGAs, such as the Virtex-5, and Spartan-6, there is no clear winner between P-CORDIC and Flat-CORDIC. Para-CORDIC never outperforms P-CORDIC and Flat-CORDIC, but still represents an improvement over standard CORDIC implementations. Furthermore, Para-CORDIC can be deeply pipelined for applications where high throughput is the main design goal.