Automatic FFT code generation for FPGAs with high flexibility and human readability

This paper describes a Fast Fourier Transform (FFT) core which uses code generation to create optimised Hardware Description Language (HDL) code for a radix-2, decimation in time FFT. The generated code is designed to be human readable, vendor non-specific and is available in both Verilog and VHDL languages. A choice of In-place or Multipath Delay Commutator (MDC) architectures is provided. Selectable architectures and generic, readable HDL code make the core highly flexible for use in different applications and with different hardware platforms. The implementation of the available architectures and their relative merits are discussed. Maximum clock speed and resource requirements are examined and compared.