Information processing using an electro-optic oscillator subject to multiple delay lines

Reservoir Computing (RC) is a promising general framework for processing high bit-rate data streams [1]. The basic idea behind RC is the expansion of an original complex problem (input data), onto the higher dimensional phase space of the reservoir, in which it is expected that a simple linear separation can solve the problem formulated by the input data. Standard reservoirs are composed of a large number of randomly interconnected nodes. It has been recently shown that a single nonlinear node with delayed feedback substitutes an entire network of nodes maintaining similar processing power [1]. By defining virtual nodes as delayed states that reside in the delay line, it is enough to have only one hardware node in the setup.Experimental realizations of this approach to RC has been recently implemented in photonics using semiconductors laser with delayed feedback [2,3]. The obtained results are similar or even outperform the state of the art for prediction of time series or speech recognition. In spite of these encouraging results, a single nonlinear node with delayed feedback has a limited memory capacity. The memory capacity is a key property of the reservoir computers that allows the processing of dynamical signals. Tasks that require high memory capacities are until now unattainable with photonic reservoir computers. In this work we have added extra delay lines to the nonlinear node to increase the memory capacity. The equation that governs our electro-optical delayed system with multiple delays is given by the following equation:x t x t β γ I t 2 ( ) = - ( ) + sin ( ( ) + Σ w x ( t - τ ) + ψ ), i i i 1 where β is the feedback gain, γ is the input scaling, I is the input signal, ψ is the phase of the nonlinearity, and wi and τi determine the strength and the length of the feedback lines.Actually, we have found that the Memory capacity increases with the number of delay lines allowing the pro- essing of high demanding tasks (see Fig.1 right). To test the computational power of the multiple delay approach we have implemented two standard tests: the NARMA test that consist on the output calculation of a noise driven nonlinear iteration, and the delayed PARITY test that consist on the calculation of the parity of a binary input for a given delay δ. Both tasks are memory demanding and we report through numerical simulations how the addition of the multiple delay lines outperform the results obtained with standard RC. In the NARMA case we obtain a prediction error of 5%, that clearly improves the error of 14% achieved with standard RC. In the PARITY case we can extend the area of good performance until δ =15 while the standard RC is limited to δ =6.