Title :
Design of a SoC platform for digital media processing
Author :
Yuhong, Yang ; Shibao, Zhang ; Chen Yingqi
Author_Institution :
Shanghai Jiao Tong Univ., China
Abstract :
In this paper we present the design of a HDTV decoder SoC platform which is integrated with IP cores such as MIPs CPU, HDTV video decoder, video processor, OSD and many peripheral IP devices. Cores can be integrated with the platform through non-glue wrappers. By estimating the bus and memory access bandwidth we can manage the data path effectively. It is also much flexible to append new functions without changing the system structure. So the SoC architecture fits a wide application of digital media processing.
Keywords :
high definition television; system-on-chip; video coding; HDTV decoder; IP cores; SoC; bus access bandwidth; digital media processing; memory access bandwidth; Access protocols; Bridges; Control systems; Costs; Decoding; Design methodology; HDTV; Memory management; Microcontrollers; Productivity;
Conference_Titel :
VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on
Print_ISBN :
0-7803-9005-9
DOI :
10.1109/IWVDVT.2005.1504616
