DocumentCode :
1938018
Title :
Design of fault-tolerant cellular arrays on multiple-valued logic
Author :
Kamiura, Naotake ; Hata, Yutaka ; Yamato, Kazuharu
Author_Institution :
Fac. of Eng., Himeji Inst. of Technol., Hyogo, Japan
fYear :
1994
fDate :
25-27 May 1994
Firstpage :
297
Lastpage :
304
Abstract :
This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array
Keywords :
cellular arrays; logic testing; many-valued logics; fault-tolerant cellular arrays; multiple-valued logic; single-level array; stuck-at-0 fault; testability; three-level array; two-level array; Buildings; Circuit faults; Circuit testing; Design for testability; Fault tolerance; Iterative algorithms; Logic arrays; Logic design; Switches; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-5650-6
Type :
conf
DOI :
10.1109/ISMVL.1994.302187
Filename :
302187
Link To Document :
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