DocumentCode
1938042
Title
Full sensitivity and test generation for multiple-valued logic circuits
Author
Dubrova, E.V. ; Gurov, D.B. ; Muzio, J.C.
Author_Institution
Dept. of Comput. Sci., Victoria Univ., BC, Canada
fYear
1994
fDate
25-27 May 1994
Firstpage
284
Lastpage
288
Abstract
The notion of full sensitivity in a multiple-valued logic (MVL) circuit is introduced. A formalization of this notion using a specially defined operator, called mutual exclusion, is given. An expression of full sensitivity in the functional base of J.B. Rosser and A.R. Turquette (1952) is presented. The usefulness of this functional transformation with respect to test generation for MVL circuits is investigated
Keywords
logic testing; many-valued logics; full sensitivity; multiple-valued logic circuits; mutual exclusion; test generation; Algebra; Calculus; Circuit faults; Circuit synthesis; Circuit testing; Computer science; Fault detection; Logic circuits; Logic testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on
Conference_Location
Boston, MA
Print_ISBN
0-8186-5650-6
Type
conf
DOI
10.1109/ISMVL.1994.302189
Filename
302189
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