Test generation based on dynamic search space reductions

Techniques for selecting optimum sensitization paths in a logic circuit and for reducing backtrackings using a heuristic function in the form of a work load are described. The test generation algorithm, which has some resemblance to PODEM, reduces the number of backtrackings by early detection of conflicts in assignments of line values. The techniques described have deeper look-ahead capabilities than other algorithms and reduce the length of the backward consistency drive using the concepts of free and biased lines. Critical to the method is a nine-value, single-fault calculus, constituting a superset of the five values used in the classic D-algorithm. The premise of the five-value D-algorithm is that reconvergent fanout mandates a search over all subnetworks forward from the fault point. In contrast, if there exists a test that includes a single path, sensitized in terms of the nine-value calculus to a network output, this test will be justified by the backward consistency drive