Loss modeling and optimization for monolithic implementation of the three-level buck converter

This paper presents parameter extraction based loss modeling to reduce the high-order design space for the three-level buck converter optimized for monolithic implementation. Loss models derived from simulation extracted parameters are presented to reduce model complexity while maintaining accurate loss predictions. The design space is reduced further by analysis of converter characteristics. An optimization approach is applied to select the inductor, the switching frequency, and the sizes of the power devices and the gate drive stages. The loss model and the optimization approach are validated for a 3.7-to-1.15 V, 4 MHz, 2 A converter through detailed circuit simulations in a 0.18 μm CMOS process.