Global multi-level reduction technique for nonlinear simulation of high-speed interconnect circuits

Author

Gunupudi, P. ; Khazaka, Rami ; Dounavis, A. ; Nakhla, M. ; Achar, R.

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

fYear

2001

fDate

2001

Firstpage

259

Lastpage

262

Abstract

Presents two approaches for simulation of large interconnect networks with linear/nonlinear terminations. The first approach is suitable in forming macromodels of interconnect networks in order to use them repeatedly in different configurations. The second approach is a nonlinear time-domain circuit reduction technique that reduces the whole interconnect network including the nonlinear/linear terminations. This method is independent of the number of ports in the system

Keywords

VLSI; circuit CAD; circuit simulation; high-speed integrated circuits; integrated circuit interconnections; integrated circuit modelling; time-domain analysis; VLSI; computer-aided design techniques; global multi-level reduction technique; high-speed interconnect circuits; linear terminations; macromodels; nonlinear simulation; nonlinear terminations; ports; time-domain circuit reduction technique; Circuit simulation; Degradation; Design automation; Integrated circuit interconnections; Nonlinear equations; Reduced order systems; Signal design; Time domain analysis; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2001

Conference_Location

Cambridge, MA

Print_ISBN

0-7803-7024-4

Type

conf

DOI

10.1109/EPEP.2001.967659

Filename

967659