Title :
Verification of a DSP IP cores by model checking
Author :
Nguyen, Hoang Nam ; Candaele, B. ; Sarlotte, M. ; Antoine, C. ; Emeriau, S.
Author_Institution :
Thales Communications
Abstract :
This paper describes an experience in applying formal techniques to the verification of the IP cores composing a DSP. We discuss the application methods and highlight the complementary aspect with traditional simulation. The paper concludes with comments on the results and a discussion on further improvements of the methods elaborated in this experience.
Keywords :
digital signal processing chips; formal verification; DSP IP cores; formal verification; model checking; Adaptive arrays; Adaptive signal processing; Analytical models; CMOS technology; Circuit simulation; Digital signal processing; Formal verification; Signal design; State-space methods; Testing;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2002. Seventh IEEE International
Print_ISBN :
0-7803-7655-2
DOI :
10.1109/HLDVT.2002.1224440
