Title :
Modeling shared-via decoupling in a multi-layer structure using the CEMPIE approach
Author :
Cui, Wei ; Fan, Jun ; Luan, Shaofeng ; Drewniak, James L.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
The CEMPIE approach, a circuit extraction technique based on a mixed-potential integral equation, has been applied to model multi-layer structures including power and signal layers. Power-bus noise mitigation effects due to a decoupling capacitor were studied for several cases with different spacing between the capacitor and an integrated circuit (IC). Modeling results indicate that the capacitor sharing a common via with the IC power/ground pins is superior; viz., it results in the lowest power-bus noise under similar conditions
Keywords :
circuit simulation; equivalent circuits; high-speed integrated circuits; integral equations; integrated circuit modelling; integrated circuit noise; power supply circuits; surface mount technology; CEMPIE approach; SMT; circuit extraction technique; decoupling capacitor; integrated circuit modeling; mixed-potential integral equation; multi-layer structure; power layers; power-bus noise mitigation; shared-via decoupling; signal layers; Capacitors; Circuit testing; Electromagnetic compatibility; Equivalent circuits; Integral equations; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit noise; Pins; Surface-mount technology;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2001
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-7024-4
DOI :
10.1109/EPEP.2001.967660
