Design oriented analysis of package power distribution system considering target impedance for high performance microprocessors

Author

Mandhana, Om P.

Author_Institution

Somerset Design Center, Motorola Corp., Austin, TX, USA

fYear

2001

fDate

2001

Firstpage

273

Lastpage

276

Abstract

This paper presents an efficient design methodology to realize the output impedance at the high performance microprocessor core equal to or less than the target impedance to reduce the mid-frequency core noise. Based on the frequency domain analysis of the lumped model of the package power distribution network (PPDN), a systematic method of estimating capacitance and associated parasitics of decoupling capacitors used in the distributed model of the PPDN is described. The simulation results of the analytical method show good correlation with the SPICE simulation results of the distributed PPDN model to reduce the output impedance at the core

Keywords

SPICE; capacitors; circuit CAD; circuit simulation; electric impedance; frequency-domain analysis; integrated circuit design; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; microprocessor chips; power supply circuits; PPDN; SPICE simulation; capacitance; decoupling capacitors; design methodology; design oriented analysis; distributed PPDN model; frequency domain analysis; lumped model; microprocessor core; microprocessors; mid-frequency core noise; output impedance; package power distribution network; package power distribution system; parasitics; simulation; target impedance; Analytical models; Design methodology; Frequency domain analysis; Impedance; Microprocessors; Noise reduction; Packaging; Power distribution; Power system modeling; Power systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2001

Conference_Location

Cambridge, MA

Print_ISBN

0-7803-7024-4

Type

conf

DOI

10.1109/EPEP.2001.967662

Filename

967662