Design optimization methodology for simultaneous bidirectional interface

Author

de Araujo, D.N. ; Cases, M. ; Pham, N.

Author_Institution

IBM Corp., Austin, TX, USA

fYear

2001

fDate

2001

Firstpage

295

Lastpage

298

Abstract

This paper describes an electrical design optimization methodology for a high-speed point-to-point source-synchronous simultaneous bidirectional interface. These physical links are typically used to interconnect multiple processor subsystems to build symmetric multi-processor (SMP) systems, as well as to connect input/output (I/O) subsystems across relatively long distances. Major design issues such as attenuation, crosstalk, delay skew, impedance control and inter-symbol interference (ISI) are discussed for long and parallel external interconnections

Keywords

circuit optimisation; crosstalk; delays; electric impedance; integrated circuit interconnections; integrated circuit packaging; intersymbol interference; multiprocessor interconnection networks; printed circuit design; I/O subsystems; ISI; SMP systems; attenuation; crosstalk; delay skew; design issues; design optimization methodology; electrical design optimization methodology; high-speed source-synchronous simultaneous bidirectional interface; impedance control; input/output subsystems; inter-symbol interference; multiple processor subsystems interconnection; parallel external interconnections; physical links; point-to-point source-synchronous simultaneous bidirectional interface; simultaneous bidirectional interface; symmetric multi-processor systems; Attenuation; Bandwidth; Clocks; Communication cables; Crosstalk; Design optimization; Driver circuits; Integrated circuit interconnections; Jitter; Power system interconnection;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2001

Conference_Location

Cambridge, MA

Print_ISBN

0-7803-7024-4

Type

conf

DOI

10.1109/EPEP.2001.967667

Filename

967667