Synthesis of multi-variable MVL functions using hybrid mode CMOS logic

Author

Chang, Yeong-Jar ; Lee, Chung Len

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1994

fDate

25-27 May 1994

Firstpage

35

Lastpage

41

Abstract

This paper presents a new scheme for synthesizing any multi-variable MVL (Multi-Valued Logic) function. The scheme utilizes a hybrid approach, i.e. a combination of the current mode and the voltage mode CMOS circuits, to synthesize MVL functions. Due to better utilization of circuit components, it can reduce the transistor count (cost) of the synthesized circuits about one half as compared with those using the MIN-MAX gates and literals or the T-gates. Also, an extra noise margin added in the design eliminates the need of the threshold detection circuit to recover the signal in this scheme

Keywords

logic design; many-valued logics; MIN-MAX gates; MVL functions; Multi-Valued Logic; extra noise margin; hybrid mode CMOS logic; literals; multi-variable; synthesized circuits; threshold detection circuit; CMOS logic circuits; CMOS process; CMOS technology; Charge coupled devices; Circuit noise; Circuit synthesis; Costs; Multivalued logic; Programmable logic arrays; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on

Conference_Location

Boston, MA

Print_ISBN

0-8186-5650-6

Type

conf

DOI

10.1109/ISMVL.1994.302222

Filename

302222