Title :
Area-time model for synthesis of non-pipelined designs
Author :
Jain, R. ; Mlinar, M.J. ; Parker, A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
A mathematical model is presented for predicting the area-time tradeoff curve for nonpipelined data paths given a data-flow graph and a module set. Specifically, it examines operator cost and delay to predict the lower bound noninferior area-time curve. The model has been validated against designs generated by a program which synthesizes nonpipelined data paths.<>
Keywords :
circuit CAD; area-time tradeoff curve; data-flow graph; delay; lower bound noninferior area-time curve; mathematical model; nonpipelined data paths; operator cost; register transfer level; Clocks; Contracts; Delay; Flow graphs; Humans; Mathematical model; Multiplexing; Predictive models; Resource management; Wiring;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122460
