Title :
Multi-output timed Shannon circuits
Author :
Thornton, Mitchell A. ; Drechsler, Rolf ; Miller, D. Michael
Author_Institution :
Mississippi State Univ., MS, USA
Abstract :
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability are also included. Experimental results are given and analyzed for these techniques
Keywords :
binary decision diagrams; circuit optimisation; logic CAD; low-power electronics; multivalued logic circuits; timing; low power optimization technique; multi-output timed Shannon circuits; overall circuit switching probability; power reduction; synthesis approach; Binary decision diagrams; Boolean functions; Circuit synthesis; Cost function; Data structures; Logic circuits; Minimization methods; Power dissipation; Signal mapping; Switching circuits;
Conference_Titel :
VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on
Conference_Location :
Pittsburgh, PA
Print_ISBN :
0-7695-1486-3
DOI :
10.1109/ISVLSI.2002.1016873
