DocumentCode :
1938864
Title :
FPGA implementation of Gaussian noise generator
Author :
Kalatchikov, Alexander A. ; Streltsov, Gennady G.
Author_Institution :
Siberian State Univ. of Telecommun. & Inf., Novosibirsk, Russia
fYear :
2004
fDate :
1-5 July 2004
Firstpage :
100
Abstract :
A Gaussian noise generator is developed on FPGA using Box-Muller method. By means of accumulations, the central limit theorem is applied to the Box-Muller output Gaussian distribution. VHDL description of the unit and the test bench are written. Synthesis and simulation of FPGA implementation are made.
Keywords :
Gaussian distribution; Gaussian noise; circuit simulation; field programmable gate arrays; hardware description languages; Box-Muller output Gaussian distribution; FPGA implementation; FPGA simulation; FPGA synthesis; Gaussian noise generator; VHDL description; central limit theorem; Field programmable gate arrays; Gaussian distributions; Gaussian noise; Hardware design languages;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Materials, 2004. Proceedings. 5th Annual. 2004 International Siberian Workshop on
Print_ISBN :
5-7782-0463-9
Type :
conf
DOI :
10.1109/PESC.2004.241133
Filename :
1358307
Link To Document :
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