Design and implementation of high-speed asynchronous communication ports for VLSI multicomputer nodes

The authors present the design of synchronizing communication ports for a communication coprocessor chip. These ports minimize the probability of synchronization failure and support communication at a very high rate relative to the limits of the implementation technology. The scheme presented does not require any lines in the link in addition to the data lines and does not require byte-per-byte handshaking. The design includes a synchronizer and a high-performance FIFO (first-in, first-out) buffer. This design is particularly well-suited for VLSI implementation and, for a given technology, can support higher communication speeds than previous synchronizer designs.<>