Impact of technology scaling in the clock system power

Author

Duarte, David ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

2002

fDate

2002

Firstpage

52

Lastpage

57

Abstract

The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is briefly reviewed while a comprehensive framework for the estimation of systemwide (chip level) and clock sub-system power as function of technology scaling is presented. This framework is used to study and quantify the impact that various intensifying concerns associated with scaling (i.e., increased leakage currents, increased interwire capacitance) will have on clock energy and their relative impact on the overall system energy. The results obtained indicate that clock power will remain a significant contributor to the total chip power, as long as techniques are used to limit leakage power consumption

Keywords

VLSI; capacitance; clocks; integrated circuit design; integrated circuit interconnections; leakage currents; low-power electronics; microprocessor chips; timing circuits; VLSI design; chip level power; clock distribution circuitry; clock energy model; clock generation circuitry; clock network power model; clock sub-system power; clock system power; interwire capacitance; leakage currents; leakage power consumption; microprocessors; scaling models; system-wide power; technology scaling; Capacitance; Clocks; Energy consumption; Flip-flops; Integrated circuit modeling; Inverters; Microprocessors; Power generation; Power system modeling; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on

Conference_Location

Pittsburgh, PA

Print_ISBN

0-7695-1486-3

Type

conf

DOI

10.1109/ISVLSI.2002.1016875

Filename

1016875