Title :
High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph
Author :
Ohsawa, Naotaka ; Hariyama, Masanori ; Kameyama, Michitaka
Author_Institution :
Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
This paper proposes a high-performance field programmable VLSI processor (FPVLSI), in which a bit-serial processing element (PE) array is introduced to reduce the complexity of programmable interconnection networks. Therefore, the area and delay of a switch block in the interconnection network can be greatly reduced. Moreover, direct allocation of a control/data flow graph is employed where only a single node is mapped into a PE so that the wiring complexity is greatly reduced. The FPVLSI with 4400 PEs is designed in a 0.35 μm CMOS process. The performance of the FPVLSI is evaluated to be 28 times higher than that of the typical FPGA when executing the 16-point FFT
Keywords :
CMOS digital integrated circuits; VLSI; circuit complexity; data flow graphs; fast Fourier transforms; integrated circuit layout; microprocessor chips; pipeline processing; programmable circuits; 0.35 micron; 16-point FFT; ASICs; CMOS process; bit-serial processing element array; control/data flow graph; direct allocation; field programmable VLSI processor; programmable interconnection network complexity; single node mapping; switch block; wiring complexity; CMOS process; Field programmable gate arrays; Flow graphs; Intelligent systems; Intelligent vehicles; Multiprocessor interconnection networks; Programmable logic arrays; Switches; Very large scale integration; Wiring;
Conference_Titel :
VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on
Conference_Location :
Pittsburgh, PA
Print_ISBN :
0-7695-1486-3
DOI :
10.1109/ISVLSI.2002.1016881
