Title :
Field Isolation Using Shallow Trenches for Submicron CMOS Technology
Author :
Zwicker, G. ; Lange, P. ; Staudt-Fischbach, P. ; Windbracke, W.
Author_Institution :
Fraunhofer-Institut fÿr Mikrostrukturtechnik, Dilienburger Str. 53, D-1000 Berlin 33, Federal Republic of Germany
Abstract :
This paper presents a shallow trench isolation technique using plasma etching, LPCVD oxide fill, and planarization. This novel planarization technique applying X-ray lithography and isotropic O2-plasma etch needs no additional mask for block resist patterning over large isolation areas. MOSFETs have been fabricated showing nearly zero channel width loss and no threshold voltage shift down to 0.8 ¿m channel width.
Keywords :
CMOS technology; Etching; Isolation technology; MOSFETs; Planarization; Plasma applications; Plasma x-ray sources; Resists; Threshold voltage; X-ray lithography;
Conference_Titel :
Solid State Device Research Conference, 1989. ESSDERC '89. 19th European
Conference_Location :
Berlin, Germany
