A 1.2 V built-in architecture for high frequency on-line Iddq/delta Iddq test

Author

Dragic, Srdjan ; Margala, Martin

Author_Institution

Electr. & Comput. Eng. Res. Facility, Alberta Univ., Edmonton, Alta., Canada

fYear

2002

fDate

2002

Firstpage

148

Lastpage

153

Abstract

A novel low-voltage design of Iddq/delta Iddq architecture suitable for a Built-In-Self-Test (BIST) implementation with analog, digital or mixed-signal cores is proposed. In testing mode, the architecture performs a non-functional Iddq and delta Iddq test which enables a more accurate fail/pass decision. A 1.2 V high-frequency current amplifying cell is developed as a central part of the Iddq/delta Iddq current monitor. With a sensitivity of less than 200 nA, the monitor achieves a gain-bandwidth product of 6.8 GHz, a low frequency current gain of 48 dB, and a high linearity for input current range (-15 μA, 15 μA). Its functionality and high performances are verified in experimental simulations. The Iddq fault detector has been implemented in a 0.13 μm CMOS technology with 1.2 V power supply

Keywords

CMOS integrated circuits; built-in self test; electric current measurement; fault diagnosis; integrated circuit testing; low-power electronics; -15 to 15 muA; 0.13 micron; 1.2 V; 48 dB; BIST; CMOS technology; Iddq/delta Iddq architecture; analog cores; bridging faults; delta Iddq test; digital cores; fail/pass decision; fault detection; gain-bandwidth product; high-frequency current amplifying cell; input current range linearity; low frequency current gain; low-voltage design; mixed-signal cores; nonfunctional Iddq test; open faults; Built-in self-test; CMOS technology; Condition monitoring; Fault detection; Frequency; Gain; Linearity; Performance evaluation; Power supplies; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on

Conference_Location

Pittsburgh, PA

Print_ISBN

0-7695-1486-3

Type

conf

DOI

10.1109/ISVLSI.2002.1016891

Filename

1016891