Title :
A proven embedded DRAM compiler for deep submicron logic processes and system-on-a-chip ASIC designs
Author :
Tsang, Tony ; Rodriguez, Bertha ; Haag, Gerry ; Crafts, Harold
Author_Institution :
Inventra, Mentor Graphics Corp., Beaverton, OR, USA
Abstract :
This paper covers the motivations for and the advantages of using an embedded DRAM compiler technology within a standard deep submicron logic process for System-on-a-Chip (SoC). We also discuss the bit cell design and the memory architecture, as well as the automation software and methodology used in the construction of the DRAM compiler. Silicon results from the test chips are favorable. This approach makes economical and time-to-market sense, therefore it can be a viable high-performance and area-efficient option in the embedded DRAM technology
Keywords :
DRAM chips; VLSI; application specific integrated circuits; embedded systems; integrated circuit design; logic CAD; memory architecture; SoC; area-efficient option; automation software; bit cell design; deep submicron logic process; deep submicron logic processes; embedded DRAM compiler; embedded DRAM technology; memory architecture; system-on-a-chip ASIC designs; time-to-market; Application specific integrated circuits; Counting circuits; Design automation; Design methodology; Economic forecasting; Graphics; Logic design; Process design; Random access memory; System-on-a-chip;
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-4980-6
DOI :
10.1109/ASIC.1998.722901
