An algorithm for the allocation of functional units from realistic RT component libraries

Existing algorithms in high-level synthesis (HLS) typically assume a direct mapping of hardware description language (HDL) operators to RT units. This assumption simplifies synthesis to generic RT components, but prevents effective use of complex databook components, custom designed cells, previously synthesized RT modules and RT module generators. We present an algorithm for allocation in HLS for reuse of existing RT-level components. This approach can be used to customize HLS tools to user-specific RT libraries. The experiments show improvements of 10-37% in area over conventional approaches