An algorithm for the allocation of functional units from realistic RT component libraries

Author

Ang, Roger ; Dutt, Nikil

Author_Institution

Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA

fYear

1994

fDate

18-20 May 1994

Firstpage

164

Lastpage

169

Abstract

Existing algorithms in high-level synthesis (HLS) typically assume a direct mapping of hardware description language (HDL) operators to RT units. This assumption simplifies synthesis to generic RT components, but prevents effective use of complex databook components, custom designed cells, previously synthesized RT modules and RT module generators. We present an algorithm for allocation in HLS for reuse of existing RT-level components. This approach can be used to customize HLS tools to user-specific RT libraries. The experiments show improvements of 10-37% in area over conventional approaches

Keywords

circuit analysis computing; resource allocation; specification languages; HDL operators; HLS tools; RT module generators; complex databook components; custom designed cells; direct mapping; existing RT-level components; functional unit; functional unit allocation; hardware description language; high-level synthesis; previously synthesized RT modules; realistic RT component libraries; register-transfer components; synchronous circuits; user-specific RT libraries; Adders; Books; Circuit synthesis; Computer science; Delay effects; Design optimization; Hardware design languages; High level synthesis; Libraries; Logic design;

fLanguage

English

Publisher

ieee

Conference_Titel

High-Level Synthesis, 1994., Proceedings of the Seventh International Symposium on

Conference_Location

Niagara-on-the-Lake, Ont.

Print_ISBN

0-8186-5785-5

Type

conf

DOI

10.1109/ISHLS.1994.302325

Filename

302325