Title :
Performance enhancements in BOLD using ´implications´
Author :
Hachtel, G. ; Jacoby, R. ; Moceyunas, P. ; Morrison, C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
Abstract :
Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these implications has resulted in performance-enhanced versions, ESPRESSOMLT2 and MLTAUT2, of the two cornerstone tools of the BOLD system, ESPRESSOMLT (multilevel logic minimizer based on tautology checking) and MLTAUT (multilevel logic verifier). The relationship between the implied values and the intermediate don´t care set is presented. Then it is shown how this relationship can be exploited to reduce the number of tautology calls and the number of leaves in the binary recursion tree of tautology checking. A parallelized version MLTAUT2P, which runs on a Sun 3/75 LAN, is discussed. ESPRESSOMLT2, is expected to have speedups of up to a factor of 20 and the parallelized version a factor of over 100.<>
Keywords :
logic CAD; logic testing; many-valued logics; ESPRESSOMLT2; MLTAUT2; MLTAUT2P; implied network values; multilevel logic minimizer based on tautology checking; multilevel logic synthesis; multilevel logic verifier; parallelized version; performance-enhanced versions; tautology calls; Calculus; Intelligent networks; Jacobian matrices; Local area networks; Logic arrays; Logic circuits; Network synthesis; Programmable logic arrays; Sun; Uninterruptible power systems;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122470