A globally static rate optimal scheduling for recursive DSP algorithms

A set of techniques for rate-optimal scheduling of recursive DSP algorithms is presented. The underlying microprocessor system is based on the RISC architecture. The retiming process evenly distributes the delays and optimizes the scheduling time of each iteration. The unfolding of recursive data flow graph exploits intraiteration and interiteration parallelism, and the schedule can be more compacted. It is shown that after evenly retiming and unfolding with the optimal unfolding factor, a fully-extended precedence graph is generated, which can be scheduled in rate-optimal by a simple contiguous scheduling. The optimal unfolding factor is equal to the delay counts of the critical loop