DocumentCode :
1941451
Title :
A blur-range test structure of collimation-controller-integrated silicon shadow mask for three-dimensional surface patterning with sputtering
Author :
Morishita, Satoshi ; Kubota, Masanori ; Mita, Y. Oshio
Author_Institution :
Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan
fYear :
2012
fDate :
19-22 March 2012
Firstpage :
66
Lastpage :
70
Abstract :
This paper proposes a test structure for development of collimation-controller-integrated three-dimensional shadow mask to control pattern blurs by isotropic deposition such as sputtering. The collimator was intelligently employed to both suppress and intentionally introduce the blurring, depending on the substrate position. Consequently, we have successfully patterned Titanium electrodes over 225μm-deep, 720μm-wide trenches by 15μm-wide gaps, which have not been obtainable with standard 3-D shadow mask. The purpose of the test structure is to quantify blurring range by collimator to optimize its aperture widths to control deposition angles by mask design. Clear relationship between blur-range and the gap was observed and shown to be predictable by its geometry (similitude of triangles).
Keywords :
collimators; sputtering; three-dimensional integrated circuits; 3D shadow mask; blur-range test structure; collimation-controller-integrated silicon shadow mask; collimation-controller-integrated three-dimensional shadow mask; collimator; deposition angle; geometry; isotropic deposition; quantify blurring; sputtering; substrate position; three-dimensional surface patterning; titanium electrodes; Collimators; Metals; Sputtering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2012 IEEE International Conference on
Conference_Location :
San Diego, CA
ISSN :
1071-9032
Print_ISBN :
978-1-4673-1027-7
Type :
conf
DOI :
10.1109/ICMTS.2012.6190615
Filename :
6190615
Link To Document :
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