A novel test structure for FEOL device CCTG CBCM measurement in advanced 28nm technology

In the advanced CMOS technology nodes, overlap capacitance (Cov), gate fringing capacitance (Cf) and contact-to-gate capacitance (Cctg) have been increasingly important components of transistor parasitic. Accurate Cov could be extract from MOSFET Cgc curve with metal routing de-embedded structure. But Cf and Cctg could not be extracted and separated clearly with traditional AC testkey. Traditionally, Cctg and Cf are simulated and extracted by 3D solver such as Raphael simulator but lack of the correlation between Silicon and simulation. In this paper, we introduce CBCM into MOSFET FEOL Cctg and Cf measurement and extraction. With good capacitance measurement resolution of CBCM methodology and specially designed test structurers, Cctg and Cf can be successfully measured and extracted without mega routing of multiplier device. The test structures and extraction methodology are described in this paper, the extraction results from a 28 nm process is also presented. This is the first published paper in MOSFET transistor FEOL parasitic (Cf+Cctg) measurement from 28 nm process real Si.