A Biologically Plausible Neuron Circuit

A neuron circuit is presented which can mimic the operation of a spiking neuron cell. A current mirror configuration allows the temporal summing of synaptic inputs, which are subsequently stored as a charge packet on the gate of a CMOS inverter: the inverter is coupled to a second inverter and feedback is used to facilitate re-setting the cell after firing. Charge leakage from the gate of the inverter, via a reverse biased p-n junction, provides a membrane decay time constant comparable with what is observed in biological neurons. Breadboard experiments and simulation results are presented to demonstrate the functionality of the neuron circuit.