Doubly folded transistor matrix layout

A flexible module generator that lays out transistor net lists is presented. The formulation of this layout problem as a two-dimensional folding problem is novel. The folding algorithm uses an elegant hierarchical divide-and-conquer technique. The aspect ratio and pin positions can be controlled within a wide range, while the area remains approximately constant. Accurate control of the aspect ratio and pin positions is important in combination with top-down floorplanning. The mask generator uses a small library of adaptable transistors with parameters like length, width, positions of the terminals, and an optional diffusion implant. Compared to other automated layout approaches, the module generator makes smaller and more flexible layouts. The layout of the modules can be customized with respect to all major design parameters.<>