The VLSI area of high throughput linear filters of moderate order using binary weighted arithmetic

The area of linear filters in a VLSI model using binary weighted arithmetic is analyzed for real-time high throughput conditions and moderate filter order. A block parallel FIR structure is introduced with area linear in rate f by using parallel nibble-serial multipliers, while classical IIR structures are shown to grow quadratically with f. A sizing method is introduced to reduce the multiplier area of direct form IIR filters. Applying parallel multipliers to scattered look-ahead (SLA) is shown to ideally reduce area to f lg f, but changing parallel data format increases growth to f^4/3lg^2/3f. Block SVD filters are improved over classical, but remain weakly quadratic in f. Both incremental block direct form and incremental block SVD of parallel second order sections grow with f^4/3, but if their re-timing registers are discounted they become linear in f