Device Design of a High Voltage BiCMOS IC

A new high voltage (H. V) npn bipolar transistor for H. V BiCMOS IC´s has been developed which is fully compatible with conventional low valtage n-well CMOS process. The npn transistor employs n-well of low valtage (L.V) CMOS as the collector drift region and it acts as the self-isolation region as well. The narrow self-aligned base is a result of double diffusion. The device has shown a high performene, i.e, hFE of 100, fT of 31 MHz and BVceo of greater than 300 V. It is expected that complaentary H. V npn and pnp transistors of this type can be integrated with H.V and L. V CMOS and bipolar devices on a same chip by Silicon wafer Direct Bonding (SDB)/ SOT technology.