DocumentCode
1942934
Title
Design and ASIC Implementation of High-Speed DDC
Author
Li, YuJing ; Liu, Lintao ; Huang, Xu ; Zhang, Ruitao ; Li, Ruzhang
Author_Institution
Sichuan Inst. of Solid State Circuits, Chongqing, China
fYear
2011
fDate
5-7 Aug. 2011
Firstpage
365
Lastpage
368
Abstract
This paper presents a High-speed Digital Down Converter, in which speed is improved and hardware is saved with the traditional Distributed Arithmetic. The presented NCO based on the modified distributed arithmetic and the filter bank based on polyphase reaLizations of FIR filters have been implemented. The DDC´s input sample rate can reach 10MSPS in the 200MHz system clock. The simulation results indicate that the SFDR of DDC presented in this paper can reach to about 70dB.
Keywords
FIR filters; application specific integrated circuits; channel bank filters; convertors; distributed arithmetic; oscillators; ASIC; FIR filters; distributed arithmetic; filter bank; frequency 200 MHz; high-speed digital down converter; numeric control oscillator; polyphase realizations; Baseband; Filter banks; Finite impulse response filter; Hardware; Mathematical model; Mixers; DDC; High-speed; modified cordic Arithmetic;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital Manufacturing and Automation (ICDMA), 2011 Second International Conference on
Conference_Location
Zhangjiajie, Hunan
Print_ISBN
978-1-4577-0755-1
Electronic_ISBN
978-0-7695-4455-7
Type
conf
DOI
10.1109/ICDMA.2011.96
Filename
6052027
Link To Document