Latch-Up Free VLSI CMOS Circuits Considering Power-On Transients

Power-on latch-up is depending on circuit design and technology. The use of an epilayer increases the latch-up hardness of conventional CMOS (LOGIC) while for n-well CMOS with VBB generator (DRAM) the latch-up suszeptibility is increased because of the capacitive voltage divider in the periphery and the high effective substrate shunt resistance. Therefore protection circuits provide latch-up free operation.