Title :
A High Performance Liquid-Nitrogen CMOS SRAM Technology
Author :
Sun, J.Y.-C. ; Klepner, S. ; Taur, Y. ; Hanafi, H. ; Restle, P. ; Bucelot, T. ; Petrillo, K. ; Dennard, R. ; Schuster, S. ; Chappell, T. ; Chappell, B. ; Heidel, D.
Author_Institution :
IBM Research Division, Thomas J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598, U.S.A.
Abstract :
A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5¿m-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6,¿m optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated.
Keywords :
Boron; CMOS technology; Lithography; Nitrogen; Optical interconnections; Random access memory; Silicides; Temperature; Titanium; Voltage;
Conference_Titel :
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location :
Montpellier, France