Characterisation of Narrow-Spaced Isolation in a Twin Retrograde Well Submicron CMOS Process

Small N⁺-P⁺ spacings have been realised using twin retrograde well technology in combination with an advanced isolation scheme. In this paper suppression of field transistor leakage currents is demonstrated by simulation and experimental results. The results show that an N⁺-P⁺ spacing of 2.5 ¿m can be realised without increased narrow-width effects in adjacent transistors.