A real-time 3D disparity-map acquisition hardware architecture for a multi-sliding-window-operation

As requirements of 3D contents have been increased, a matching algorithm to obtain a disparity-map becomes vibrant research field. This processing includes a multi-sliding-window-operation (MSWO) which requires high memory and processing-time consumption. In this paper, we propose an effective hardware architecture with convergence of on-chip memory and shift registers, and parallelized cores. We utilize census as a matching algorithm and a 7 by 7 window in a 160 by 90 image, with search range length of 42. We synthesize on Vertex 5 from Xilinx, operating at 100 MHz clock. Our proposed method has lower memory consumption, and search range length times faster than previous one.