Title :
Resource constrained RTL partitioning for synthesis of multi-FPGA designs
Author :
Vootukuru, Madhavi ; Vemuri, Ranga ; Kumar, Nand
Author_Institution :
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Abstract :
In this paper we address the problem of partitioning register level designs for implementation on multiple FPGAs. The partitioner uses a modified multi-way Fiduccia-Mattheyses algorithm. Cost estimation functions needed by the partitioner to estimate the resources needed by the design on a FPGA have been developed. The methodology for estimation of resources on an FPGA (function generators, flip-flops and CLBs), and partitioning of the design are discussed in detail
Keywords :
circuit CAD; estimation theory; field programmable gate arrays; high level synthesis; logic partitioning; cost estimation functions; modified multi-way Fiduccia-Mattheyses algorithm; multi-FPGA designs; multiple FPGA implementation; register level designs; resource constrained RTL partitioning; Contracts; Costs; Decision support systems; Field programmable gate arrays; Flip-flops; High level synthesis; Libraries; Partitioning algorithms; Pins; Signal generators;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568066
