Dependability and life time enhancements for nano-electronic systems

According to recent investigations on fault mechanisms in nano-scale integrated circuits, they suffer from wear-out effects that limit their life time seriously. For application that combine a long life time and safety-critical functionality, means of fault compensation, de-stressing and eventual self repair are therefore becoming a must. While built-in self repair (BISR) is state-of-the-art in memory blocks and in FPGA, it is much more difficult to implement in irregular logic blocks. In this paper, we introduce a circuit architecture that combines capabilities of self repair and de-stressing. The necessary overhead can be estimated, and limitations as well as “single points of failure” are discussed.