DocumentCode :
1943359
Title :
Formal techniques for hardware allocation
Author :
Mendias, J.M. ; Hermida, R. ; Fernandez, M.
Author_Institution :
Dept. de Inf. y Autom., Univ. Complutense de Madrid, Spain
fYear :
1997
fDate :
4-7 Jan 1997
Firstpage :
161
Lastpage :
165
Abstract :
Hardware reusability is a key aspect of behavioral synthesis which is mainly based on the possibility of implementing several operators with a single module. This shared use of resources is heavily dependent on the ability of the synthesis tool to identify candidate operators to be merged. Some ideas for the creation of a uniform framework where the semantics of hardware modules can be formally expressed are presented in this paper. The application to hardware allocation through symbolic manipulation is also addressed
Keywords :
computational linguistics; formal specification; high level synthesis; resource allocation; symbol manipulation; behavioral synthesis; candidate operators identification; hardware allocation; hardware modules; hardware reusability; semantics; symbolic manipulation; synthesis tool; Character recognition; Circuits; Delay; Design methodology; Hardware; High level synthesis; Job shop scheduling; Joining processes; Libraries; Proposals;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
0-8186-7755-4
Type :
conf
DOI :
10.1109/ICVD.1997.568070
Filename :
568070
Link To Document :
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