A Fully Characterised Process for Titanium Silicide by RTA for One Micron CMOS

A fully characterised process for self-aligned titanium silicide by RTA is described. Factors influencing formation; surface pre-clean, time-temperature schedules and ambient choice are all discussed. The sensitivity of the formation process to implanted arsenic is also described and a model presented for this effect. The technique is proven by its inclusion in a one-micron trench isolated CMOS process schedule and electrical results for devices and circuits thus fabricated are presented.