Impact Ionization and Freeze-Out Model for Simulation of Low Gate Bias Kink Effect in SOI-MOSFETs Operating at Liquid He Temperature

A 0.4 mum p-channel silicon-on-insulator (SOI) metal-oxide-field-effect-transistor (MOSFET) is measured at 300 K and 4 K. Finite difference two dimensional numeric device simulations are performed at these temperatures to provide physical insight about the mechanisms that lead to the observed cryogenic effects at liquid Helium temperature. The MOSFET subthreshold slope is measured as 88 mv/dec at 300 K and is observed to have a drain bias dependence at 4 K ranging from 30 mv/dec at low source-to-drain (V_SD) voltage (0.05 V) to 10 mv/dec at high V_SD (3.3 V). A kink in the current is furthermore observed at low gate bias (1.35 V) and drain bias above 2 V. The numeric simulations indicate that incomplete ionization of dopants at cryogenic temperatures and impact ionization significantly affect the device behavior in the subthreshold region of operation at 4 K. Specifically, for a low source-to-gate (V_SG) bias (V_SG = 1.35 V, which is near subthreshold) the former affects the base current level, and the latter along with the incomplete ionization gives rise to a current kink for high drain biases (V_sd > V). The simulation techniques to handle the numerical challenges related to device modeling at 4 K are also presented.