DocumentCode :
1944311
Title :
InGaAs Single- and Dual-Gate High-Speed FETs : Preparation and Performance
Author :
Steiner, K. ; Ntikbasanis, K. ; Seiler, U. ; Heime, K. ; Kuphal, E.
Author_Institution :
Universitÿt Duisburg, Halbleitertechnik/Halbleitertechnologie, Sonderforschungsbereich 254, D-4100 Duisburg. F.R.G
fYear :
1988
fDate :
13-16 Sept. 1988
Abstract :
The preparation and performance of self-aligned single-and dual-gate InGaAs JFETs is discussed. Single-gate InGaAs JFETs exhibit maximum extrinsic transconductance of 350, 275 and 140 mS/mm at a gate length of 0.5, 1.5 and 3.5 ¿m, respectively. High overall potential barriers at the channel substrate heterointerface are necessary for control of threshold voltage uniformity over a wide range of gate lengths. For the first time device behaviour of self-aligned dual-gate InGaAs JFET is demonstrated.
Keywords :
Etching; FETs; Fabrication; Indium gallium arsenide; Indium phosphide; JFETs; Lattices; Substrates; Transconductance; Zinc;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location :
Montpellier, France
Print_ISBN :
2868830994
Type :
conf
Filename :
5436896
Link To Document :
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