Design of FinFET SRAM Cells Using a Statistical Compact Model

Author

Lu, Darsen D. ; Lin, Chung-Hsun ; Yao, Shijing ; Xiong, Weize ; Bauer, Florian ; Cleavelin, Cloves R. ; Niknejad, Ali M. ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA

fYear

2009

fDate

9-11 Sept. 2009

Firstpage

1

Lastpage

4

Abstract

A study of designing FinFET-based SRAM cells using a compact model is reported. Parameters for a multi-gate FET compact model, BSIM-MG are extracted from fabricated n-type and p-type SOI FinFETs. Local mismatch in gate length and fin width is calibrated to electrical measurements of 378 FinFET SRAM cells. The cell design is re-optimized through Monte Carlo statistical simulations. Variation in readability, writability and static leakage of the cell are studied.

Keywords

MOSFET; Monte Carlo methods; SRAM chips; integrated circuit modelling; silicon-on-insulator; statistical analysis; BSIM-MG; FinFET SRAM cell design; Monte Carlo statistical simulations; SiO₂-Si; electrical measurement; multigate FET compact model; n-type SOI FinFETs; p-type FinFETs; readability; static leakage; statistical compact model; writability; Electric variables measurement; Electronic mail; FETs; FinFETs; Instruments; Length measurement; MOSFETs; Monte Carlo methods; Random access memory; Semiconductor process modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on

Conference_Location

San Diego, CA

ISSN

1946-1569

Print_ISBN

978-1-4244-3974-8

Electronic_ISBN

1946-1569

Type

conf

DOI

10.1109/SISPAD.2009.5290234

Filename

5290234