CGASC-a silicon compiler for the CMOS gate array

Summary form only given. A new silicon compiler for the CMOS gate array named CGASC, for automating the complex task of chip designing, is presented. CGASC accepts the hardware description language AHPL (a hardware programming language) or VHDL (VHSIC hardware description language) as input and compiles the described circuit into the CMOS gate array device. The automation of the compiler includes the chip size estimation, the floor planning, and placement, the channel ordering and routing, and the layout generation. Active modules of CGASC include a logic optimizer, a modular circuit partitioner, a hierarchical floor planner, a pseudocontinuous cell allocator, a global router, and a detailed router. The design goal of CGASC was to synthesize a complex digital circuit from behavioral-level input to mask-level output with as little manual intervention as possible. The development of CGASC proves the feasibility of using hardware description languages as the input media of hardware compilers. During applications, CGASC estimates chip size and allows users to select the most appropriate chip based on the basis of the availability of IC markets. Online interactive routing is also available to facilitate the zoom-in/out of a critical routing area and the modification of routing configuration