Simulation-Based Lithography Optimization for Logic Circuits at 22nm and Below

Lithography optimization based on physical simulation is a powerful technique to achieve good image quality at subwavelength feature sizes with small Rayleigh k₁ factors. For the lower end of the 32 nm logic node, even with immersion scanners, the Rayleigh k₁ factor is below 0.32. The 22 nm logic node should begin with minimum pitches of approximately 70 nm, requiring some form of double patterning to maintain k₁ above 0.25. For certain types of circuits such as NAND Flash, highly optimized scanner illuminators are well-known to improve feature fidelity. However, logic patterning has been more difficult than NAND Flash patterning because random logic was designed with complete "freedom" compared to the very regular patterns used in memory. Logic layouts with bends and multiple pitches resulted in larger rules, un-optimized illumination, and poorly understood process windows with little control of context-dependent "hot spots". The introduction of logic design styles which use strictly one-directional lines for the critical levels now provides the opportunity for illumination optimization. Gridded Design Rules (GDR) have been demonstrated to give area-competitive layouts at existing 90, 65, and 45 nm logic nodes while reducing CD variability. These benefits can be extended to les 32nm logic using selective double pass patterning.