Dependence of Injection Velocity and Capacitance of Si Nanowires on Diameter, Orientation, and Gate Bias: An Atomistic Tight-Binding Study

We present a simulation study of Si nanowire (NW) transistor devices for logic applications using an atomistic tight-binding (TB) model for the electronic structure calculation, self consistently coupled to a two-dimensional Poisson solver for the solution of the electrostatics. A semiclassical ballistic model is used for the transport calculation. The average carrier velocity and the capacitance of cylindrical NMOS and PMOS NWs with diameters from 3 nm to 12nm, in the [100], [110] and [111] transport orientations are calculated at different gate bias. The capacitance of all wires is only a function of the wires´ diameter, and in all cases is degraded from the oxide capacitance by ~20%. The carrier velocities increase with increasing gate biases. The carrier velocity of PMOS NWs in the [110] and [111] orientations is a strong function of the wires´ diameter, whereas that of [100] and [111] NMOS and [100] PMOS devices has only a weak dependence on the diameter.