Title :
Wafer level packages (WLPs) using anisotropic conductive adhesives (ACAs) solution for flip-chip interconnections
Author :
Kim, Il ; Jang, Kyung-Woon ; Son, Ho-Young ; Kim, Jae-Han ; Paik, Kyung-Wook
Author_Institution :
Dept. of Mater. Sci. & Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon
Abstract :
In this study, wafer level packages (WLPs) using anisotropic conductive adhesives (ACAs) solution for flip-chip interconnections have been newly developed and the effects of process parameters on the wafer level package performance were investigated. At first, the effect of coating process parameters such as blade gap and temperature were investigated for uniform thickness coating without voids and bubbles on a Au bumped wafer. After solvent drying and the subsequent singulation of a B-stage ACA solution coated wafer, singulated chips were flip-chip assembled on organic substrates using a thermo-compression bonding method. The reliabilities of flip chip assemblies using WLP were evaluated in terms of high temperature/humidity, and pressure cooker test and compared with those of conventional anisotropic conductive film (ACF) package. In high temperature/humidity reliability test, there was no difference of flip chip reliabilities between two types of flip chip assemblies. Furthermore, in pressure cooker test (PCT), WLP using ACAs solution showed better reliability than conventional ACF package.
Keywords :
coating techniques; conductive adhesives; flip-chip devices; gold; integrated circuit testing; substrates; wafer level packaging; B-stage ACA solution coated wafer; anisotropic conductive adhesives solution; anisotropic conductive film package; bumped wafer; coating process parameters; flip chip assemblies; flip-chip interconnections; humidity reliability test; organic substrates; pressure cooker test; singulated chips; solvent drying; thermo-compression bonding; wafer level packages; Anisotropic magnetoresistance; Assembly; Coatings; Conductive adhesives; Flip chip; Humidity; Packaging; Temperature; Testing; Wafer scale integration;
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2008.4549973