Digital IF decimation filters for 3G systems using pipeline/interleaving architecture

This paper presents efficient of IF decimation filters architecture using pipeline/interleaving (PI) technique in which the amount of multiplications is reduced by 50%. The decimation filters are important blocks in software radio terminals to process different communications standards like GSM, IS-95, and UMTS. These kinds of blocks are needed to process the I, and Q components on the digital down-converter. The proposed architecture is evaluated by MATLAB. This evaluation shows that the proposed structures can be utilized in a multimode fashion. The frequency response of the decimator filter for each standard is analyzed and the frequency response for the decimator filter using Pl architectures is also evaluated. The new architecture offers saving of 50% the amount of multiplications compare to the traditional implementation.